Methods and apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuits

ABSTRACT

In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode. The output of the dynamic input circuit is used to gate the predischarging device.

FIELD OF THE INVENTION

The present invention relates to methods and apparatus for bipolarelimination in silicon-on-insulator (SOI) domino circuits.

DESCRIPTION OF THE PRIOR ART

Silicon-on-insulator (SOI) technology is an enhanced silicon technologycurrently being utilized to increase the performance of digital logiccircuits. Utilizing SOI technology designers can increase the speed ofdigital logic integrated circuits while reducing their overall powerconsumption. These advances in technology will lead to the developmentof more complex and faster computer integrated circuits that operatewith less power.

Complementary metal oxide semiconductor (CMOS) compound domino logic(CDL) circuits or domino circuits are known. CMOS domino circuitsprovide a logical function, such as a NOR function or a NAND function,providing a logical output signal responsive to a plurality of inputsignals. Many domino circuits Include a P-channel field effecttransistor that is clocked to precharge an intermediate node causing theoutput to go to a predetermined logic state.

As shown in FIG. 1. SOI semiconductors include a thin layer of siliconplaced on top of an insulator, such as silicon dioxide (SiO₂) or glass,and a MOS transistor built on top of this structure. The main advantageof constructing the MOS transistor on top of an insulator layer is toreduce the internal capacitance of the transistor. This is accomplishedby placing the insulator oxide layer between the silicon substrate andthe impurities required for the device to operate as a transistor.Reducing the internal capacitance of the transistor increases itsoperating speed. With SOI technology faster MOS transistors can bemanufactured resulting in higher performance semiconductors for fasterelectronic devices.

Referring to FIGS. 1 and 2, there is shown the SOI FET and the parasiticbipolar device. A problem called bipolar discharge exists with SOI FETs.An inherent drawback of placing a MOS transistor on top of a SOI layeris that the MOS transistor is actually placed in parallel with a bipolarjunction transistor, as illustrated in FIG. 2. If enough current ispassed through the MOS transistor, the parasitic bipolar transistor willturn on. This causes the unwanted effect called bipolar discharge andlowers the performance of the MOS transistor.

Normally, parasitic bipolar action does not manifest itself inconventional, bulk, NMOS transistors because the base of the bipolartransistor is always kept at ground potential, keeping the bipolartransistor turned off. In the SOI FET, the body (B) of the MOS FETdevice, or base of the bipolar transistor, is floating and can becharged high by junction leakages induced when both drain (D) and source(S) terminals of the MOS FET are at a high potential. Subsequently, ifthe source (S) is pulled to a low potential, the trapped charge in thebase area (B) is available as parasitic base current. The parasitic basecurrent activates the bipolar transistor and generates a collectorcurrent at the drain terminal of the MOS FET. This collector currentflow in the bipolar junction transistor or bipolar discharge isundesirable since it causes an unintended loss of charge on the drainnode of a dynamic circuit. Such bipolar discharge reduces theperformance of the MOS SOI FET device and can result in the functionalfailure of the dynamic circuit causing the logic circuit to output awrong value.

High speed CMOS circuits often employ a domino circuit technique thatutilizes pre-charging to improve the gate speeds of the transistors.Circuit nodes are pre-charged during each clock cycle to a certainlevel. The problem with SOI FETs is that the parasitic bipolartransistor can cause bipolar discharge of pre-charged circuit nodes.

A need exists to eliminate the effect of parasitic bipolar transistorsor for bipolar elimination in precharged SOI domino circuits.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide improvedsilicon-on-insulator (SOI) domino circuits. Other objects are to providesuch SOI domino circuits substantially without negative effects and thatovercomes many of the disadvantages of prior art arrangements.

In brief, methods and apparatus are provided for bipolar elimination insilicon-on-insulator (SOI) domino circuits. Apparatus for bipolarelimination in silicon-on-insulator (SOI) domino circuit includes adomino silicon-on-insulator (SOI) field effect transistor. An input iscoupled to the domino silicon-on-insulator (SOI) field effecttransistor. A predischarging device is coupled to said dominosilicon-on-insulator (SOI) field effect transistor. The predischargingdevice is activated during a precharge mode of the domino circuit, sothat the SOI parasitic bipolar transistor is not activated.

In accordance with features of the invention, a dynamic input circuitcouples the input to the domino silicon-on-insulator (SOI) field effecttransistor. The output of the dynamic input circuit is low during theprecharge mode. The output of the dynamic input circuit corresponds tothe input during the evaluate mode. The output of the dynamic inputcircuit is used to gate the predischarging device.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention together with the above and other objects andadvantages may best be understood from the following detaileddescription of the preferred embodiments of the invention illustrated inthe drawings, wherein:

FIG. 1 is a cross sectional view illustrating a conventionalsilicon-on-insulator (SOI) N-channel field effect transistor (NFET);

FIG. 2 is a schematic diagram illustrating the conventionalsilicon-on-insulator (SOI) N-channel field effect transistor (NFET) ofFIG. 1 including a bipolar junction transistor;

FIG. 3 is a schematic diagram illustrating a predischarged dynamic gatecircuit of the preferred embodiment;

FIG. 4 is a schematic diagram illustrating the predischarged dynamicgate circuit of FIG. 3 provided for bipolar elimination insilicon-on-insulator (SOI) domino circuits of the preferred embodiment;

FIG. 5 is a schematic diagram illustrating a dynamic buffer circuit ofthe preferred embodiment;

FIG. 6 is a schematic diagram illustrating the predischarged dynamicbuffer circuit of FIG. 5 provided for bipolar elimination insilicon-on-insulator (SOI) domino circuits of the preferred embodiment;and

FIG. 7 is a schematic diagram illustrating another dynamic logic circuitfor bipolar elimination in silicon-on-insulator (SOI) domino circuits ofthe preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Having reference now to the drawings, in FIG. 3, there is shown apredischarged dynamic gate circuit generally designated by the referencecharacter 300 of the preferred embodiment. FIG. 4 illustrates thepredischarged dynamic gate circuit 300 used for bipolar elimination in asilicon-on-insulator (SOI) domino circuit generally designated by thereference character 400 of the preferred embodiment.

Predischarged dynamic gate circuit 300 includes a N-channel field effecttransistor (NFET) 302 and a P-channel field effect transistor (PFET)304. A low CLK signal turns off the clock gated NFET 302 and turns onPFET 304. A high CLK signal turns on the clock gated NFET 302 and turnsoff PFET 304. When the CLK signal is low, the OUT signal ofpredischarged dynamic gate circuit 300 is LOW regardless of the INsignal. When the CLK signal is high, the OUT is equal to the IN signal.

In FIG. 4, the silicon-on-insulator (SOI) domino circuit includes aclocked, precharge P-channel field effect transistor (PFET) 402 and asecond PFET 404 respectively coupled between a supply voltage VDD and aprecharge node XPRE. An inverter 406 is coupled between the prechargenode XPRE and the gate of PFET 404. The gate of PFET 402 receives aclock signal CLK. The source of the PFETs 402, 404 is connected to thepositive supply rail VDD. The drain of the PFETs is connected to theprecharge node XPRE. The precharge PFET 402 is turned on with low clockcycles to precharge the precharge node XPRE to a high or one levelduring the precharge mode. The precharge PFET 402 is turned off withhigh clock cycles during the evaluate mode. Domino circuit includes aPFET 408 and an N-channel FET (NFET) 410 connected between the supplyrail VDD and ground. The precharge node XPRE is connected to the gatesof the PFET 408 and NFET 410. The connection of the respective drain andsource of the PFET 408 and NFET 410 provides the output of the SOIdomino circuit at a line labeled OUT.

Domino circuit includes a plurality of stacks of series connected NFETs412, 414; 416, 418; 420, 422; and 424, 426 between the precharge nodeXPRE and a source node NCLK of a clocked NFET 430. A respectivepre-discharged PFET 432, 434, 436, and 438 is connected between groundand the source and drain connection of the respective series connectedNFETs 412, 414; 416, 418; 420, 422; and 424, 426 or nodes labeled X0,X1, X2, and X3. The pre-discharged PFETs 432, 434, 436, and 438 aregated by the output of a respective predischarged dynamic gate circuits300 coupling inputs A0, A1, A2, and A3. The purpose of thepre-discharged PFETs 432, 434, 436, and 438 is to eliminate the bipolardischarge problem in the SOI NFET.

In accordance with features of the invention, the bipolar parasiticproblem is eliminated by making certain that the SOI bipolar devicenever turns on. The circuits of the preferred embodiment ensure thatthere is never enough voltage on the base of this parasitic transistorto allow it to turn on. Discharging particular diffusions to groundutilizing the pre-discharged PFETs 432, 434, 436, and 438 guaranteesthat sufficient base voltage will not exist. The pre-discharged PFETs432, 434, 436, and 438 are turned on during the precharge mode with theCLK is low.

During the pre-charge phase the input CLK is active low, then node XPREis charged high. During the precharge phase, all inputs provided by theoutput of the predischarged dynamic gate circuits 300 are low. So duringthe pre-charge phase PFETs 432, 434, 436, and 438 are active dischargingnodes X0, X1, X2, and X3 to a P-channel threshold voltage above ground.As a result, the body voltages of NFETs 412, 416, 420 and 420 cannot getsufficiently high to activate the corresponding parasitic bipolar NPNtransistors of NFETs 412, 416, 420 and 420. As a result, the node XPREis protected from unintended discharge.

Referring to FIG. 5, there is shown a dynamic buffer circuit generallydesignated by the reference character 500 of the preferred embodiment.FIG. 6 illustrates the dynamic buffer circuit 500 utilized for bipolarelimination in silicon-on-insulator (SOI) domino circuit 600 of thepreferred embodiment. The predischarged dynamic gate circuit 300 worksin a very similar way as the dynamic buffering circuit 500 to solve thesimilar problems. In FIG. 6 the same reference numbers used in SOIdomino circuit 400 are used for similar or identical components of theSOI domino circuit 600.

Dynamic buffering circuit 500 similarly addresses the case of an inputcoming from a non-domino logic block and which might be high during thedomino circuit precharge phase. Dynamic buffering circuit 500 isarranged as a domino block where the input of concern comes in to alower NFET device 502 In an evaluate stack 504 of the new domino block.Since dynamic buffering circuit 500 is a domino circuit, its output willbe low or at a downlevel during precharge. Evaluate stack 504 includes aclocked PFET 506 AND NFET 508 connected in series with input gated NFET502 between the supply voltage VDD and ground. A precharge PFET 510 isconnected between a precharge node PRE. Dynamic buffering circuit 500includes a PFET 512 and an N-channel FET (NFET) 514 connected betweenthe supply rail VDD and ground. The precharge node PRE is connected tothe gates of the PFET 512 and NFET 514. The connection of the respectivedrain and source of the PFET 512 and NFET 514 provides the output of thedynamic buffering circuit 500.

When CLK=0, the Dynamic Buffer circuit 500 stops the IN signal frompassing through, and forces the OUT signal to be low. However, whenCLK=1, OUT signal will be equivalent to the IN signal. Since all inputsignals to domino gate are treated to be don't care during prechargestate, when CLK=0, adding dynamic buffer circuit 500 in front of thecircuit is a solution to solve this problem. All input signals are nowforced to be low during pre-charge which enables or turns on dischargeddevices PFETs 432, 434, 436 and 438 during precharge state.

FIG. 7 illustrates an alternative SOI domino circuit generallydesignated by the reference character 700 of the preferred embodiment.SOI domino circuit 700 has fewer transistors and is slightly faster thanthe SOI domino circuits 400 and 800. SOI domino circuit includes a pairof precharge PFETs 702 and 704 coupled between a supply rail VDD and aprecharge node YPRE. A PFET 706 and an NFET 708 having their gatesconnected to the precharge node YPRE are connected between VDD andground. PFET 706 and NFET 708 provide the output of SOI domino circuit700 indicated at a line labeled OUT.

FIG. 7 shows how a node XC of concern at the connection of source ofNFET 710 and drain of NFET 712 for bipolar parasitic is discharged by aPFET 714, thus eliminating the bipolar parasitic threat. PFET 716 willalways pull down the gate of the top evaluation NFET 710 duringprecharge, eliminating sneak paths. NFET 718 is a "pass gate" that isdisabled during precharge but passes the A0 input which comes fromnon-domino logic and could be high or low only during the evaluate phaseof the clock. Preferably NFET 718 is a low threshold FET, but since thisinput does not drive a ratioed circuit, it does not matter if the passedsignal only reaches VDD minus the threshold voltage Vt of NFET 718. SOIdomino circuit 700 only uses three FETs 714, 716 and 718 and the onlydelay is passing A0 through the pass gate NFET 718. The input circuitformed by FETs 714, 716 and 718 is only needed for inputs to prechargeddomino circuitry that are not guaranteed to be downlevel duringprecharge. Inputs to evaluate stacks formed by NFETs 720, 724, 726 and728 may be from domino logic and are low during the precharge phase.

In FIG. 7, A0 was used as an example with the bipolar elimination inputcircuitry 700 of the preferred embodiment, but any or all of the inputsA0, A1, A2 can use this technique. It should be understood that thedynamic gate 300 and the dynamic buffer circuit 500 can be with any orall of the inputs A0, A1, A2, A3 that are not guaranteed to be downlevelduring precharge.

It should be understood that NFETs with an inverted clock applied ontheir gates can be used Instead of PFETs 714 and 716. In fact a saferdesign results if an NFET is used for PFET 716 as to guarantee that thegate of NFET 718 is held solidly at ground instead of a threshold aboveground. Note that if A0 is a low or downlevel, it will quickly bebrought down to ground during evaluate, when the CLK goes high again. Alow threshold PFET for PFET 716 is a prudent device to use as thethreshold of the low threshold PFET 716 would be less than the normalthreshold of NFET 718. Either an NFET and PFET can be used for PFET 714since a small voltage at the source of NFET 718 would not create abipolar parasitic problem.

It should be understood that principles of the present invention applyto domino logic circuits formed of PFETs.

While the present Invention has been described with reference to thedetails of the embodiments of the invention shown in the drawing, thesedetails are not intended to limit the scope of the invention as claimedin the appended claims.

What is claimed is:
 1. A method for bipolar elimination insilicon-on-insulator (SOI) domino circuit comprising the stepsof:providing a discharging device coupled to a domino SOI field effecttransistor; coupling an input to said domino SOI field effect transistorthrough a dynamic circuit; and activating said discharging device duringa precharge mode of the domino circuit utilizing an output of saiddynamic circuit to activate said discharging device, said dynamiccircuit providing a low output during said precharge mode and saiddynamic circuit providing an output corresponding to said input duringan evaluate mode.
 2. The method for bipolar elimination insilicon-on-insulator (SOI) domino circuit as recited in claim 1 includesthe step of providing a dynamic gate circuit for said dynamic circuit.3. The method for bipolar elimination in silicon-on-insulator (SOI)domino circuit as recited in claim 2 includes the step of providing saiddynamic gate circuit formed by a pair of field effect transistors, onegated field effect transistor of said pair of field effect transistorsconnecting between said input and said domino SOI field effecttransistor.
 4. The method for bipolar elimination insilicon-on-insulator (SOI) domino circuit as recited in claim 3 includesthe step of providing another field effect transistor of said pair offield effect transistors for discharging said gated field effecttransistor.
 5. The method for bipolar elimination insilicon-on-insulator (SOI) domino circuit as recited in claim 1 includesthe step of providing a dynamic buffer circuit for said dynamic circuit.6. The method for bipolar elimination in silicon-on-insulator (SOI)domino circuit as recited in claim 5 includes the step of providing adynamic buffer circuit for said dynamic circuit; said dynamic buffercircuit comprising a domino logic block.
 7. Apparatus for bipolarelimination in silicon-on-insulator (SOI) domino circuit comprising:adomino silicon-on-insulator (SOI) field effect transistor; an inputcoupled to said domino silicon-on-insulator (SOI) field effecttransistor through a dynamic circuit; and a predischarging devicecoupled to said domino silicon-on-insulator (SOI) field effecttransistor; said predischarging device being activated during aprecharge mode of said domino circuit utilizing an output of saiddynamic circuit to activate said predischarging device, said dynamiccircuit providing a low output during said precharge mode and saiddynamic circuit providing an output corresponding to said input duringan evaluate mode.
 8. Apparatus for bipolar elimination insilicon-on-insulator (SOI) domino circuit as recited in claim 7 whereinsaid dynamic circuit includes a dynamic gate circuit, said dynamic gatecircuit includes a first field effect transistor connecting said inputto said domino silicon-on-insulator (SOI) field effect transistor. 9.Apparatus for bipolar elimination in silicon-on-insulator (SOI) dominocircuit as recited in claim 8 wherein said dynamic gate circuit includesa second field effect transistor connected between said first fieldeffect transistor and ground.
 10. Apparatus for bipolar elimination insilicon-on-insulator (SOI) domino circuit as recited in claim 7 whereinsaid dynamic circuit includes a dynamic buffer circuit.
 11. Apparatusfor bipolar elimination in silicon-on-insulator (SOI) domino circuit asrecited in claim 10 wherein said dynamic buffer circuit includes adomino logic block.
 12. Apparatus for bipolar elimination insilicon-on-insulator (SOI) domino circuit as recited in claim 2 whereinsaid precharging device is turned off during an evaluate mode of saiddomino circuit.